The electronics industry continues to strive for high-powered, high-functioning circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integration of circuits on small areas of a silicon wafer. Integrated circuits of this type are manufactured through a series of steps carried out in a particular order. Main objectives in manufacturing many such devices include obtaining a device that occupies as small an area as possible and consuming low levels of power using low supply levels, while performing at speeds comparable to speeds realized by much larger devices.
Marketplace needs have created a demand for increased fast data-storage capability in an ever-decreasing package size. For many applications, this has translated to efforts to increase the number of memory cells in a given chip size (or real estate area) but using fewer elements to implement each of the cells. The tension between attempting to increase the number of memory cells while using a smaller package, has resulted in a variety of efforts and approaches to memory cell design.
One type of fast data-storage device that has been consistently used to address such demands is high density DRAM, which is approaching an era of giga-bit scale. Technology has been developed leading to the advent of 4 Gbit DRAM which requires the minimum cell area of 0.1 .mu.m.sup.2. This degree of scaling has been enabled by advances in photolithography and memory cell technology such as complicated capacitor structures and dielectric materials. However, as the cell area decreases, process margins such as alignment tolerance have become limiting factors for developing next generation DRAM cells. In addition, the leakage current through transistors and isolations between adjacent cells increases significantly degrading refresh characteristics of devices. These problems expand with decreases in the cell area without changing basic cell layouts such as the conventional 1 M DRAM structure dating back to the late 1980's.
FIG. 1A illustrates such a conventional layout. The layout of FIG. 1A consists of 8 F.sup.2 size boundary, where F is the minimum feature size. A structure including conventional MOSFET and a stack or trench capacitor, is placed laterally in this layout.
There have been efforts to decrease the number of features, and several reports have proposed fabricating DRAM cells with significantly different layouts. One such approach proposes building DRAM cells with a 4 F.sup.2 layout. This type of structure is shown in FIG. 1B. The key benefit of this technology lies in the basic layout. Given a minimum feature size (F), the cell area is 4 F.sup.2 rather than 8 F.sup.2 for the conventional structure. Accordingly, the cell area can be reduced by one half using this type of layout.
Further, within this cell area of size-reduced layouts, large process margins can be achieved using a vertically-arranged pass transistor. Since the pass transistor is formed vertically, the channel length does not change as the cell size decreases. This long channel permits the transistor device to have low-level subthreshold currents and small drain-induced-barrier-lowering (DIBL) effects. Also, because the pass transistors in each pair of adjacent cells are not formed along an electrically intercoupled path, isolation between the pass transistors is inherent.
While the architectures of such structures show promise, the processing steps used to implement the architectures have been overly-complex. These processing proposals typically involve the introduction of complex processing steps into a less-burdensome conventional process, for the purpose of manufacturing a DRAM memory cell including a pillar-type pass transistor over a capacitor. Examples of these architectures and their proposed processing approaches are characterized in: U.S. Pat. Nos. 5,252,845 ("Trench DRAM Cell With Vertical Transistor") 5,316,962 ("Method Of Producing A Semiconductor Device Having Trench Capacitors and Vertical Switching Transistors"), and 5,102,817 ("Vertical DRAM Cell And Method"); and various papers including S. Maedada et al., VLSI Tech. Symp., p.133 (1994), and K. Sinouchi et al., IEDM Techical Digest, p.23 (1989). Some of the process problems presented by these approaches include: the epi process from the contact hole being barely controllable; the gate oxide grown from the gate (rather than the channel) causing a potential reliability problem; alignment tolerances between contact holes; and word lines that are patterned before the contact process. Even though each of the above approaches uses vertical pillar structure that permits construction of the word line via the self-alignment, these approaches have the tendency of decreasing process margins more than conventional processes.
Accordingly, there is a need for a semiconductor manufacturing process for constructing a memory cell that reduces the complexity typically associated with vertically-arranged transistors in DRAM cells, maintains process margins of conventional processes, and overcomes problems associated with the above- mentioned prior art.